1. Field of the Invention
The invention relates to an apparatus for testing or burning-in semiconductor chips, and more particularly to such an apparatus for testing or burning-in semiconductor chips with the chips being disposed on a common wafer, that is to say, without chips being diced into individual chips.
2. Description of the Related Art
A semiconductor device has been conventionally fabricated in the following steps of: forming a plurality of chips on a silicon wafer by means of photolithography technique; separating chips into individuals by so-called "dicing" step; wire-bonding; sealing each chip with resin; and packaging each of chips. Then, an electrical load is applied to the thus packaged chips for a short period of time under high temperature atmosphere, for instance, at 125 degrees centigrade. The appliance of an electrical load to chips makes it possible to initially find inferior products. This step is called a "burn-in" step, and is carried out in manufacturing steps of almost all semiconductor devices.
As mentioned above, thermal load and electrical load are given to each of chips in the burn-in step. In addition to this, a measurement of electrical properties of chips is also carried out in the burn-in step in these days. This step is called a "test and burn-in" step. The purpose of the test and burn-in step is to find and hence remove inferior chips at an initial stage with high accuracy and in a short period of time. In a step prior to or after a burn-in step, or in a final step, a tester is often used for removing inferior devices and/or controlling qualities of devices. Such a tester for testing devices are used after each of chips has been packaged as mentioned so far.
On the other hand, function tests for chips have been carried out with a prober and a tester before each chips is packaged, that is, while each chips is still disposed on a wafer. However, it is quite difficult to carry out such function tests at high speed.
In a conventional burn-in process, a burn-in step is carried out after each of chips has been packaged as a final product, as aforementioned. This means that steps of wire-bonding and/or sealing with resin are in vain for chips which have been found to be inferior by a burn-in step, causing the increase of costs.
In addition, a method such as MCM in which naked chips not sealed with resin are directly positioned on a substrate has been widely used, and thus it is desired to improve a burn-in process applicable to chips mounted on a wafer by the above mentioned method. It is in particular desired to establish a burn-in process in which chips are to be burnt-in before a plurality of chips formed on a wafer are diced into individual chips, because such a process makes it possible to carry out a burn-in step at earliest among manufacturing steps to thereby reduce the manufacturing costs.
As aforementioned, the tests for devices have conventionally been carried out after a chip was packaged as a final product. This results in a problem that chips which have been found inferior in the tests cannot be repaired with an appropriate means such as a redundancy circuit.
In other words, with respect to high integration, it is necessary for a memory having large capacity such as 64 MDRAM to be positioned in parallel for testing, because it takes tens of hours to test such a memory. Thus, it is in turn necessary to install additional driver circuits and/or increase capacity of such driver circuits, causing a manufacturing cost of a tester to be increased.
With respect to the increased operation speed of a device, it is preferable for a measurement system including a tester to be positioned as closely as possible to a device. However, a conventional tester has a limit in positioning closely to a device, and in addition such positioning causes a manufacturing cost to be high.
As aforementioned, simple function tests have been carried out with a prober with chips being disposed on a wafer or without dicing chips into individuals. However, this method is accompanied by a problem that a high-speed testing is impossible due to a large parasitic capacity of a probe card.
Thus, it is desired to establish a method in which it is not necessary to remodel a tester into an expensive one, and by which it is possible to carry out high-speed function tests for a plurality of parallel disposed chips with such chips being disposed on a wafer or without dicing chips into individuals.